Building a Virtual Framework for Networked Recon gurable Hardware and Software Objects

Logic and I O Block The logic block used in an FPGA strongly in uences the FPGA speed and area e ciency While many di erent logic blocks have been used in FPGAs most current commercial FPGAs are using logic blocks based on look up tables LUTs Accordingly in our research we will only build abstract logic block for those LUT based FPGAs One abstract basic logic block is shown in Fig It contains a K input LUT we choose K in the example to implement com binational logic a D ip op to implement sequential logic and a multiplexer to choose the output The pin locations of an abstract logic block are chosen randomly because they will be mapped to the real pin locations of the client FPGA later Combination of abstract basic logic blocks can be used to describe a series of commercial logic blocks such as those used in Altera K and K FPGAs Xilinx and series